The Cortica architecture was designed to fit a client’s needs. It brings together three Intesym technologies: a massively-parallel Symbiotic processing architecture (Polymer) optimised for reconfigurable idemetric processing, interfacing to conventional computers via a SATAnet derivative interface to provide an on-line “Intelligent Storage” database device.
Idemetric Processing homepage
Cortica can be used for all of the functions to which Intesym idemetric processing is suited, such as image similarity, object recognition, and scene understanding.
Most image processing systems are implemented in software on workstations and servers. In many situations this is acceptable, but there are various situations where a custom hardware approach is preferable. For example:
As Cortica is a reconfigurable processor, there needs to be an element of programmability. Overall functionality is provided by software on a collection of Polymer Symbiotic processors. Custom circuitry is provided to accelerate important functions. For this kind of work, Symbiotic processing has numerous advantages over conventional CPU architectures:
Cortica appears as a hard disc to a host computer, and so access to it is simple through any operating system’s ordinary device drivers and filing-system calls. It can be installed internally in an enclosure’s standard 3.5"/5.25" drive bay or connected externally via eSATA.
Cortica supports the processing of large full-colour (24-bit RGB) images and searching through large databases very quickly. The following table lists the preliminary specification for a typical Cortica-based image similarity database server.
† For full-colour megapixel query images and a full database of one million full-colour megapixel images, returning similarity statistics against every database image for every query. Higher throughputs and lower latencies will occur for smaller images and/or smaller databases, or if only a subset of results (e.g. the best matches) is required.
A parallel computing architecture, scalable from embedded systems to supercomputers, efficiently handling fine-grain concurrency levels of hundreds of thousands.
Variants include 16- to 64-bit general purpose systems, transmuteable instructions, and arbitrary precision arithmetic.
A case for a new architecture